1. Field of the Invention
The present invention is directed to semiconductor manufacturing. More specifically, this invention relates to a damascene structure having a reduced permittivity and a manufacturing method thereof.
2. Description of the Related Art
Recent developments in semiconductor process technology have led to a decrease in device dimension and an increase in signal speed. With smaller and faster devices, conductive interconnect structures in devices play an increasingly significant role in device performance. A major area of concern is the resistance and capacitance (RC) delay associated with the interconnect structures of devices. As device dimensions become smaller, the RC delay causes greater signal propagation delay and has a larger effect on overall operating speed. Moreover, the RC delay also contributes to power dissipation.
Various efforts have been made to minimize the RC delay effect of interconnections. For example, one way to minimize the RC delay is by reducing the resistance of the interconnect structures. Aluminum interconnects had been widely used in semiconductor devices for decades. With the reduction in chip size, however, aluminum interconnects have been largely replaced by copper, which has a lower resistance than aluminum, in order to the RC delay. As a result, copper processing technology, e.g., copper Back End Of line (BEOL) processing, has been extensively developed. Copper BEOL processing involves damascene interconnection processes, in which trenches are formed in a layer of dielectric material, and copper is used to fill the trenches to form the interconnection. However, there is still a need to further reduce the RC delay of the interconnection, and improve the signal speed.